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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
FEATURES
* Four LVCMOS/LVTTL outputs, 15 typical output impedance * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Output frequency Range: 56MHz - 175MHz * VCO Range: 560MHz - 700MHz * RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.52ps (typical) design target Phase noise: Offset Noise Power
GENERAL DESCRIPTION
The ICS840004-01 is a 4 output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 156.25MHz, 125MHz, and 62.5MHz. The ICS840004-01 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The ICS840004-01 is packaged in a small 20-pin TSSOP package.
IC S
100Hz ............... -94.9 dBc/Hz 1kHz ............. -119.6 dBc/Hz 10kHz ............. -128.9 dBc/Hz 100kHz ............. -129.2 dBc/Hz * Full 3.3V or 3.3V core/2.5V output supply mode * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
FREQUENCY SELECT FUNCTION TABLE
F_SEL1 F_SEL0 0 0 1 1 0 1 0 1
FOR
ETHERNET FREQUENCIES
M/N Ratio Value 6.25 5 2.5 5 Output Frequency (25MHz Ref.) 156.25 125 62.5 12 5
Inputs M Divider N Divider Value Value 25 4 25 25 25 5 10 5
BLOCK DIAGRAM
OE Pullup F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL XTAL_IN Pulldown 25MHz
PIN ASSIGNMENT
2
F_SEL0 nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT
OSC
XTAL_OUT TEST_CLK Pulldown
0
F_SEL1:0
1 Phase Detector
00 01 10 11
Q0
1
VCO
0
N /4 /5 /10 /5
Q1
ICS840004-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
Q2
M = /25 (fixed)
Q3
G Package Top View
MR
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840004AG-01 www.icst.com/products/hiperclocks.html REV. B JANUARY 3, 2006
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Type Description Frequency select pin. LVCMOS/LVTTL interface levels. No connect. Selects between the cr ystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the otuputs to go low. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Power supply ground. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 15 typical output impedence. Output supply pin. Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 9 3 4 5 Name F_SEL0 nc nXTAL_SEL TEST_CLK OE Input Unused Input Input Input Pulldown Pulldown Pullup Pullup
6
MR
Input
Pulldown
7 8 10 11, 12 13, 19 14, 15 17, 18 16 20
nPLL_SEL VDDA VDD XTAL_OUT, XTAL_IN GN D Q3, Q2, Q1, Q0 VDDO F_SEL1
Input Power Power Input Power Output Power Input
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance VDD, VDDA, VDDO = 3.465V VDD, VDDA = 3.465V, VDDO = 2.625V Test Conditions Minimum Typical 4 TBD TBD 51 51 15 Maximum Units pF pF pF k k
8400042AG-01
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REV. B JANUARY 3, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 90 8 5 Maximum 3.465 3.465 3.465 2.625 Units V V V V mA mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current Input Low Current OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDO = 3.3V5% VDDO = 2.5V5% VDDO = 3.3V or 2.5V5% -150 -5 2.6 1.8 0.5 Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 5 150 Units V V A A A A V V V
IIL
VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuits.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal.
840004AG-01 www.icst.com/products/hiperclocks.html REV. B JANUARY 3, 2006
Test Conditions
Minimum
Typical 25
Maximum
Units MHz
Fundamental 50 7 1 pF mW
3
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fOUT t sk(o) Parameter Output Frequency Range Output Skew; NOTE 1, 3 156.25MHz @ Integration Range: 1.875MHz - 20MHz 125MHz @ Integration Range: 1.875MHz - 20MHz 62.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 56 TBD 0.52 0.65 0.55 TBD 400 Typical Maximum 175 Units MHz ps ps ps ps ms ps %
t jit(O)
RMS Phase Jitter (Random); NOTE 2
tL tR / tF
PLL Lock Time Output Rise/Fall Time
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fOUT t sk(o) Parameter Output Frequency Range Output Skew; NOTE 1, 3 156.25MHz @ Integration Range: 1.875MHz - 20MHz 125MHz @ Integration Range: 1.875MHz - 20MHz 62.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 56 TBD 0.48 0.59 0.53 TBD 450 Typical Maximum 175 Units MHz ps ps ps ps ms ps %
t jit(O)
RMS Phase Jitter (Random); NOTE 2
tL tR / tF
PLL Lock Time Output Rise/Fall Time
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8400042AG-01
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REV. B JANUARY 3, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 62.5MHZ @3.3V
0 -10 -20 -30 -40 -50
1Gb Ethernet Filter 62.5MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.55ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -170 -180 -190 100 1k -160
Phase Noise Result by adding 1Gb Ethernet Filter to raw data
10k 100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 62.5MHZ @2.5V
0 -20 -30 -40 -50
1Gb Ethernet Filter 62.5MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.53ps (typical)
-10
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding 1Gb Ethernet Filter to raw data
100k 1M 10M 100M
REV. B JANUARY 3, 2006
OFFSET FREQUENCY (HZ)
840004AG-01
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 125MHZ @3.3V
0 -20 -30 -40 -50
10Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.65ps (typical)
-10
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k 100k -160
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
1M 10M 100M
TYPICAL PHASE NOISE AT 125MHZ @2.5V
0 -20 -30 -40 -50
OFFSET FREQUENCY (HZ)
10Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.59ps (typical)
-10
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -160 -170 -180 -190 100
8400042AG-01
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
1k 10k 100k 1M 10M 100M
REV. B JANUARY 3, 2006
OFFSET FREQUENCY (HZ)
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ @3.3V
0 -20 -30 -40 -50
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps (typical)
-10
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k 100k -160
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
1M 10M 100M
TYPICAL PHASE NOISE AT 156.25MHZ @2.5V
0 -20 -30 -40 -50
OFFSET FREQUENCY (HZ)
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.48ps (typical)
-10
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
REV. B JANUARY 3, 2006
-160
OFFSET FREQUENCY (HZ)
840004AG-01 www.icst.com/products/hiperclocks.html
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDA, VDDO
SCOPE
Qx
VDD, VDDA
SCOPE
VDDO GND
Qx
LVCMOS
GND
LVCMOS
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
V
DDO
Qx
2
Phase Noise Mask
V
DDO
Qy
f1
Offset Frequency
f2
2 tsk(o)
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT SKEW
V
DDO
80% 20% tR
80% 20% tF
Q0:Q3 t PW
t
2
Clock Outputs
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
8400042AG-01
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B JANUARY 3, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840004-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332
ICS840004-01
Figure 2. CRYSTAL INPUt INTERFACE
840004AG-01
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REV. B JANUARY 3, 2006
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
LAYOUT GUIDELINE
Figure 3 shows a schematic example of the ICS840004-01. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used. The C1=22pF and
Logic Control Input Examples
3.3V
C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1K pullup or pulldown resistors can be used for the logic control input pins.
Set Logic Input to '1'
RU1 1K
3.3V
Set Logic Input to '0'
RU2 Not Install
R3 36
Zo = 50 Ohm
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
U1 LVCMOS 1 2 3 4 5 6 7 8 9 10 F_SEL0 nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT 20 19 18 17 16 15 14 13 12 11
3.3V
R4 36
Zo = 50 Ohm
3.3V R2 10
VDDA C3 10uF 3.3V C4 0.01u C6 0.1u
C5 0.1u
LVCMOS
ICS840004-01 XTAL_OUT C2 22pF X1 XTAL_IN C1 22pF
FIGURE 3. ICS840004-01 SCHEMATIC EXAMPLE
8400042AG-01
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REV. B JANUARY 3, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5C/W 73.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004-01 is: 3085
840004AG-01
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153
8400042AG-01
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REV. B JANUARY 3, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840004-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Marking ICS840004A01 ICS840004A01 ICS40004A01L ICS40004A01L Package 20 Lead TSSOP 20 Lead TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP Shipping Packaging tube tape & reel tube tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS840004AG-01 ICS840004AG-01T ICS840004AG-01LF ICS840004AG-01LFT
NOTE: Par ts that are ordered with an LF suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840004AG-01 www.icst.com/products/hiperclocks.html REV. B JANUARY 3, 2006
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